Verification Infrastructure

Built and maintained critical verification infrastructure tools and systems that support processor verification workflows across multiple product lines at Synopsys. These tools enable automation, improve productivity, and provide visibility into verification health.

Co-Simulation

Prototyped co-simulation environment that revolutionized processor verification methodology for Synopsys ARC processors

C-Forge

ML-based configuration space optimization tool that reduced verification effort by 50%+ for ARC Processor IP

Log Anomaly Detector

LLM-powered failure triage with MCP access to logs, traces, and FSDB waveforms

Dashboard

Built project dashboards for verification health monitoring with Grafana and Streamlit

FSDB Tracer

FSDB tracer tool that generates human-readable instruction execution traces from FPGA emulator waveforms

Other Contributions

Regression automation system for ARC processors in use for 10+ years with OGE to LSF migration

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Duration: 2012 — Present
Role: Lead Developer & Architect