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Random Program Generators (RPGs)

Designed, developed, and led the development of 3 RPGs for processor-level verification from scratch, serving various generations of ARC processors. They follow different design philosophies addressing the shortcomings of each other. They serve as the backbone of verification infrastructure, supporting 50+ verification engineers across multiple product lines from time to time in Synopsys' ARC processor family.

G1: Offline Test Generator

Perl-based offline instruction generator for ARC processors. Primary RPG for 6+ years supporting 20-30 verification engineers

G2: State Aware Generator

SystemVerilog-based processor state-aware test generation framework supporting 50+ verification engineers. Generates billions of instructions daily

G3: C Based Scenario Generator

C-based scenario generator focusing on high-level test scenarios using CSmith. Introduces additional randomization dimensions for processor verification

Technical Challenges​

  • Handling complex multi-issue scheduling constraints
  • Providing a flexible API framework for a wide range of test scenarios
  • Managing different processor variants and configurations
  • Supporting all processor features including multicore systems, caches, cache coherency, MMU, MPU, VLIW, SIMD, and multi-issue pipes

Impact​

  • Boosted the productivity of verification engineers across multiple parallel product lines
  • Significantly reduced test development time

Duration: Dec 2011 — Present

Role: Lead Developer & Product Manager

Users: 50+ verification engineers