5 docs tagged with "SystemVerilog"

ML-based configuration space optimization tool that reduced verification effort by 50%+ for ARC Processor IP using intelligent coverage optimization.

Prototyped co-simulation environment that revolutionized processor verification methodology for Synopsys ARC processors, enabling robust test development.

FSDB tracer tool that generates human-readable instruction execution traces from FPGA emulator waveforms, bridging the gap between FPGA and RTL simulation.

SystemVerilog-based processor state-aware test generation framework supporting 50+ verification engineers. Generates billions of instructions daily across ARC processor families.

End-to-end verification of ISA Coverage, Action Points, MMU, and Debug features at MLV and PLV levels for ARC processors.