6 docs tagged with "Python"

ML-based configuration space optimization tool that reduced verification effort by 50%+ for ARC Processor IP using intelligent coverage optimization.

FSDB tracer tool that generates human-readable instruction execution traces from FPGA emulator waveforms, bridging the gap between FPGA and RTL simulation.

SystemVerilog-based processor state-aware test generation framework supporting 50+ verification engineers. Generates billions of instructions daily across ARC processor families.

C-based scenario generator focusing on high-level test scenarios using CSmith. Introduces additional randomization dimensions for processor verification.

LLM-powered verification failure triage with MCP access to logs, traces, and FSDB waveforms. Evolved from a Master's thesis ML anomaly detector.

Built project dashboards for verification health monitoring. Evolved from Grafana-based to Streamlit-based solution for better automation and visualization.