6 docs tagged with "Verification"

ML-based configuration space optimization tool that reduced verification effort by 50%+ for ARC Processor IP using intelligent coverage optimization.

Prototyped co-simulation environment that revolutionized processor verification methodology for Synopsys ARC processors, enabling robust test development.

SystemVerilog-based processor state-aware test generation framework supporting 50+ verification engineers. Generates billions of instructions daily across ARC processor families.

Built project dashboards for verification health monitoring. Evolved from Grafana-based to Streamlit-based solution for better automation and visualization.

Leading Verification Best Practices team to establish standards, methodologies, and best practices across multiple product lines at Synopsys.

End-to-end verification of ISA Coverage, Action Points, MMU, and Debug features at MLV and PLV levels for ARC processors.