G2: State Aware Generator
SystemVerilog-based processor state-aware test generation framework supporting 50+ verification engineers. Generates billions of instructions daily across ARC processor families.
SystemVerilog-based processor state-aware test generation framework supporting 50+ verification engineers. Generates billions of instructions daily across ARC processor families.
AI-ML log anomaly detector using machine learning for automated failure triaging in processor verification regressions. Master's thesis project.