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Vijaya Krishna Kasula - Principal Engineer at Synopsys

Krishna

Principal Engineer (ASIC Digital Design) @ Synopsys Hyderabad

15+ years experience in Processor VerificationM.Tech in Data Science & Engineering, BITS Pilani

Hands-on verification experience of critical processor components. Improving team efficiency by proactively identifying problems and building advanced verification tools bottom-up using cutting-edge technologies. These solutions have significantly improved productivity and delivered measurable impact across multiple product lines.

Processor Verification

Deep expertise in processor architecture and verification methodologies. Proficient in complex processor features including MMU, MPU, Cache Coherency, VLIW, SIMD, and multicore systems. Skilled in coverage-driven verification, constraint-based test generation, and both PLV and MLV verification levels. Examples include designing state-aware test generators supporting complex processor features and end-to-end verification of ISA coverage, action points, and debug units.

AI/ML in Verification

Unique ability to apply machine learning techniques to verification challenges. Expertise in anomaly detection, clustering, and classification algorithms for optimization, triaging, and automation in verification workflows. Examples include building AI-ML log anomaly detectors for failure triaging, developing ML-based configuration space optimization tools, and integrating ML-based failure analysis into verification processes.

Technical Leadership

Proven capability in building scalable verification infrastructure from scratch and establishing best practices across teams. Skilled in prototyping new tools, standardizing methodologies, and leading cross-functional initiatives. Examples include leading the Verification Best Practices team, prototyping co-simulation environments that changed verification methodology, and introducing AI tools and modern development practices to verification teams.